---------------------------------------------------------------------------------
  -- Design Name : IF-ID Registers
  -- File Name   : R_If_Id.vhd
  -- Function    : IF-ID registers
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity R_If_Id is
  port (
    clk         : in  std_logic;
    reset       : in  std_logic;
    stall       : in  std_logic;  
    wrkIn       : in  std_logic;
    wrkOut      : out std_logic := '0';  
    newAddrIn   : in  word32;
    newAddrOut  : out word32
  );
end R_If_Id;

architecture behavioral of R_If_Id is
  signal sglNewAddrIn  : word32;
  signal sglNewAddrOut : word32;
  signal workSignal    : std_logic;
  signal newAddrLd   : std_logic;

begin

  sglNewAddrIn <= newAddrIn;
  newAddrOut <= sglNewAddrOut;
  newAddrLd <= workSignal and not stall;

  newAddr: GenReg32 port map ( 
    clk    => clk,
    ld     => newAddrLd,
    cl     => reset,
    regIn  => sglNewAddrIn,
    regOut => sglNewAddrOut
  );
  
  process(clk)
  begin
    if rising_edge(clk) then -- read
      if (reset = '1') then
        wrkOut <= '0';
      else
        wrkOut <= workSignal;
      end if;
    end if;
          
    if falling_edge(clk) then -- write
      workSignal <= wrkIn;
    end if;
  end process;
  
end architecture behavioral;